Design & Reuse
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198 IP
51
5.0
General Purpose Input/Output Controller
The CC-GPIO-AXI is a synthesisable Verilog model of a General Purpose Input/Output Controller. The GPIO core can be efficiently implemented on FPGA an...
52
5.0
Peripheral Direct Memory Access Controller
The CC-PDMA-APB-AHB is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...
53
5.0
Peripheral Direct Memory Access Controller
The CC-PDMA-AXI-AXI is a synthesisable Verilog model of a peripheral direct memory access controller. The PDMA core can be efficiently implemented on ...
54
5.0
Configurable System Tick Counter
The CC-SYSTICK-APB is a synthesisable Verilog model of a system tick timer counter controller. The SYSTICK core can be efficiently implemented on FPGA...
55
5.0
Configurable Timer Counter
The CC-TIMER-APB is a synthesisable Verilog model timer counter controller. The TIMER core can be efficiently implemented on FPGA and ASIC technologie...
56
5.0
Configurable Watchdog Timer
The CC-WDT-APB is a synthesisable Verilog model of a watchdog timer controller. The WDT core can be efficiently implemented on FPGA and ASIC technolog...
57
5.0
SPI Master / Slave Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
58
5.0
SPI Serial Peripheral Interface Master/Slave
The CC-SPI-APB is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...
59
5.0
SPI Slave Controller (SPI2APB, SPI2AXI, SPI2AHB Bus)
The Digital Blocks DB-SPI-S-AMBA-BRIDGE is a Serial Port Interface (SPI) Controller Verilog IP Core supporting SPI Slave Interface to APB Master Bus. ...
60
5.0
eSPI & SPI Master/Slave Controller w/FIFO (APB, AHB, or AXI Bus)
The Digital Blocks DB-eSPI-SPI-MS-AMBA is a Serial Peripheral Interface (SPI) Controller Verilog IP Core supporting the addition of Enhanced SPI (eSPI...
61
4.0
I2C Controller (AMBA APB <-> I2C)
The I2C Controller provides access to devices with I2C interface. It accepts the Read / Write commands from APB and converts it to the serial I2C acce...
62
4.0
SATA Host Controller
HCLSATAHC26113G core handles data movement between system memory and a SATA device. The core implements transport layer & link layer functions. HCLSA...
63
4.0
DDR3 Controller IP
The AXI DDR3 Controller provides access to DDR3 memory. It accepts the Read / Write commands from AXI and converts it into DDR3 access. While doing th...
64
4.0
AHB Cache Controller Core
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the...
65
4.0
AHB Compliant Nand Flash Controller
NAND Flash Controller has a built-in AHB Slave Interface, handles all sorts of Nand Flash commands, address & data sequences. It allows the users to a...
66
4.0
AHB to APB Bridge
The AHB to APB bridge is an AHB slave, providing an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are...
67
3.0
1.8V/3.3V Switchable GPIO With 3.3V I2C Open Drain & Analog in TSMC 22nm
A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation. The GPIO ce...
68
3.0
I2C Slave with AHB Master Bridge (I2C2AHB)
The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
69
3.0
I2C Slave with APB Master Bridge (I2C2APB)
The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
70
3.0
I2C Slave with AXI Master Bridge (I2C2AXI4)
The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...
71
3.0
2D Graphics Hardware Accelerator (AXI4 Bus)
The DB9200AXI4 2D Graphics Engine Verilog IP Core targets low VLSI footprint, high-performance hardware accelerated graphics applications. The DB92...
72
3.0
ChaCha20 stream cipher core
The eSi-CHACHA20 core is an easy to use CHACHA20 stream cipher hardware accelerator that is compliant with the IETF RFC7539 standard. ChaCha20, along...
73
3.0
UHS-II PHY for SD4/SD5 TSMC 12nm FF
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
74
3.0
UHS-II PHY for SD4/SD5 TSMC 16nm FF
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
75
3.0
Poly1305 core
The eSi-POLY1305 core is an easy to use POLY1305 accelerator peripheral that is fully compliant with the RFC7539 IETF standard. Poly1305, along with...
76
3.0
Combined ChaCha20 and Poly1305 core
The eSi-CHACHA20-POLY1305 core is an easy to use APB hardware accelerator peripheral that is fully compliant with the IETF RFC7539 standard Poly130...
77
3.0
Configurable AES Core
eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies. They can be configured to customer the requirements to enable a...
78
2.0
I3C Master / Slave Controller - MIPI Basic v1.0
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC ...
79
2.0
Advanced Encryption Standard (AES-128) core with AMBA AHB interface
The GRAES core implements the Advanced Encryption Standard (AES) symmetric encryption algorithm for high throughput application (like audio or video s...
80
2.0
Bi-directional AMBA AHB/AHB bridge
The bi-directional AHB/AHB Bridge is used to interconnect high-speed and low-speed AMBA AHB buses. The bridge supports synchronous clocks with any fre...
81
2.0
Gigabit Ethernet 802.3 MAC - Media Access Controller
The Gigabit Ethernet Media Access Controller with AHB Interface IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. The Gigabit Ethernet - ...
82
2.0
Elliptic Curve Cryptography (ECC) core with AMBA APB interface
The GRECC core implements Elliptic Curve Cryptography (ECC) which is used as a public key mechanism and is well suited for application in mobile commu...
83
2.0
AMBA interface for Actel MIL-STD-1553B Cores
The GR1553 is a set of AMBA AHB/APB wrappers for the Actel AX/RTAX MIL-STD-1553B cores. Wrappers for the following Actel cores are provided: Core1553B...
84
2.0
Uni-directional AMBA AHB to AHB bridge
The Uni-directional AHB to AHB bridge is used to connect two AHB buses clocked by synchronous clocks with any frequency ratio. The bridge is connected...
85
1.0
DES/TDES core
The eSi-DES block performs encryption and decryption of 64-bit words using the DES (Data Encryption Standard) and TDEA (Triple DES Encryption Algorith...
86
1.0
Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware based ...
87
1.0
Digital Down Converter core
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer. The DDS is implemented in a resource ef...
88
1.0
BitBLT Graphics Hardware Accelerator (AHB Bus)
The Digital Blocks DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to ...
89
1.0
BitBLT Graphics Hardware Accelerator (AXI Bus)
The Digital Blocks DB9100AXI3 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...
90
1.0
RSA public key cryptography with APB interface
The standard RSA module is available as an APB peripheral, where it seamlessly integrates with EnSilica's cryptography library. The peripheral can be...
91
1.0
RTP / UDP / IP Hardware Stack for H.264/H.265 NAL Video Streams Packet Processing
The Digital Blocks DB-RTP-UDP-IP-NAL IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor...
92
1.0
RTP / UDP / IP Hardware Stack for Raw, Uncompressed RGB/YUV Video Streams
The Digital Blocks DB-RTP-UDP-IP-AV IP Core is a RTP/UDP/IP Protocol Hardware Stack with MAC Layer Pre- & Post-Processors and an ARP Packet Processor ...
93
0.118
AHB system Peripheral IP, AHB - to - AHB Bridge, Soft IP
AHB to AHB bridge....
94
0.118
AHB system Peripheral IP, AHB - to - APB Bridge, Soft IP
The IP is APB Bridge between AHB bus and APB bus....
95
0.118
AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP
AHB to AXI bridge....
96
0.118
AHB system Peripheral IP, AHB - to - AXI Bridge, Soft IP
AMBA AXI to AHB Bridge....
97
0.118
AHB system Peripheral IP, AHB Arbiter, Soft IP
The IP is AHB Controller composed of ar-Biter, dECOder and Mux....
98
0.118
AHB system Peripheral IP, External Bus controller, Soft IP
External Bus Interface Controller....
99
0.118
AHB system Peripheral IP, IDE Host controller, Soft IP
IDE host controller with AHB interface....
100
0.118
AHB system Peripheral IP, Interrupt controller, Soft IP
Interrupt controller with AHB interface....